LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TRIAL2 IS
	PORT(
		CLK,RST,EN : IN STD_LOGIC;
		CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		COUT : OUT STD_LOGIC
	);
END TRIAL2;

ARCHITECTURE BHV OF TRIAL2 IS


BEGIN
	PROCESS(CLK,RST,EN)
		VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN
		IF RST = '1' THEN CQI := (OTHERS => '0');
		ELSIF CLK'EVENT AND CLK ='1' THEN	
			IF EN = '1' THEN
				IF CQI < "1001" THEN CQI := CQI + 1;
				ELSE CQI := (OTHERS => '0');
				END IF;
			END IF;
		END IF;
		
		IF CQI = "1001" THEN COUT <= '1';
			ELSE COUT <= '0';
		END IF;
		CQ <= CQI;
	END PROCESS;

END BHV;